Those young machine spirits need their rest

From what I understood, the radar systems were incompatible and that’s why despite it being on the table it wasn’t sold to the Ukrainians. That and the requirement to gather accurate surveys of the areas to be protected.

That makes a lot of sense - I wonder if they also do the SIGSEGV trick like HotSpot to know when they need to JIT the next chunk of instructions

But does it run Doom? Using CMOV instructions only?

I thought FAT binaries don’t work like that - they included multiple instruction sets with a header pointing to the sections (68k, PPC, and x86)

Rosetta to the best of my understanding did something similar - but relied on some custom microcode support that isn’t rooted in ARM instructions. Do you have a link that explains a bit more in depth on how they did that?

From what I’ve understood of this - it’s transpiling the x86 code to ARM on the fly. I honestly would have thought it wasn’t possible but hearing that they’re doing it - it will be a monumental effort, but very feasible. The best part is that once they’ve gotten CRT and cdecl instructions working - actual application support won’t be far behind. The biggest challenge will likely be inserting memory barriers correctly - a spinlock implemented in x86 assembly is highly unlikely to work correctly without a lot of effort to recognize and transpile that specific structure as a whole.